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Digital System Test and Testable Design: Using HDL Models and Architectures
Zainalabedin Navabi
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Description for Digital System Test and Testable Design: Using HDL Models and Architectures
Hardcover. Using Verilog models and test benches for implementing and explaining fault simulation and test generation algorithms, this book treats the concepts of testing and testability in digital systems, and also covers digital design practices and methodologies. Num Pages: 452 pages, 100 black & white illustrations, biography. BIC Classification: HP; PB; TJFC. Category: (P) Professional & Vocational. Dimension: 254 x 178 x 25. Weight in Grams: 1011.
This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps ... Read more
This book is about digital system testing and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses Verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps ... Read more
Product Details
Format
Hardback
Publication date
2010
Publisher
Springer
Condition
New
Number of Pages
435
Place of Publication
New York, NY, United States
ISBN
9781441975478
SKU
V9781441975478
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
About Zainalabedin Navabi
About the Author Dr. Zainalabedin Navabi is a professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Navabi is the author of several textbooks and computer based trainings on VHDL, Verilog and related tools and environments. Dr. Navabi’s involvement with hardware description languages begins in 1976, when he started the development of a register-transfer level simulator ... Read more
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