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Logic Synthesis and Verification Algorithms
Hachtel, Gary D. (University Of Colorado); Somenzi, Fabio
€ 115.27
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Description for Logic Synthesis and Verification Algorithms
Paperback. Num Pages: 596 pages, biography. BIC Classification: PBD; THR; TJFC; UGC; UMA. Category: (G) General (US: Trade). Dimension: 254 x 178 x 31. Weight in Grams: 1126.
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on ... Read more
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on ... Read more
Product Details
Format
Paperback
Publication date
2013
Publisher
Springer-Verlag New York Inc. United States
Number of pages
596
Condition
New
Number of Pages
564
Place of Publication
New York, NY, United States
ISBN
9781475770360
SKU
V9781475770360
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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