High-Level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Wang, Zheng; Chattopadhyay, Anupam
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Description for High-Level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
Hardback. Series: Computer Architecture and Design Methodologies. Num Pages: 20 black & white illustrations, 80 colour illustrations, biography. BIC Classification: TJFC; UYD. Category: (G) General (US: Trade). Dimension: 235 x 155. .
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
Product Details
Format
Hardback
Publication date
2017
Publisher
Springer Verlag, Singapore Singapore
Condition
New
Series
Computer Architecture and Design Methodologies
Number of Pages
197
Place of Publication
Singapore, Singapore
ISBN
9789811010729
SKU
V9789811010729
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
About Wang, Zheng; Chattopadhyay, Anupam
Dr.-Ing. Zheng Wang earned the Bachelor degree in physics from Shanghai Jiao Tong University (SJTU), China and Master degree in Electronic Engineering from Technische Universität München (TUM), Germany. From 2008 till 2009, he worked in the mobile sector of Infineon Technologies AG in Munich (currently Intel Mobile Communications). In 2010 he joined as a research associate in the Institute for ... Read more
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