Stock image for illustration purposes only - book cover, edition or condition may vary.
Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Chakrabarty, Krishnendu; Noia, Brandon
€ 123.28
FREE Delivery in Ireland
Description for Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Hardcover. Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Num Pages: 263 pages, 18 black & white illustrations, 115 colour illustrations, 23 black & white tables, biogra. BIC Classification: TJFC; TJFD; UYF. Category: (P) Professional & Vocational. Dimension: 243 x 157 x 16. Weight in Grams: 514.
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Product Details
Format
Hardback
Publication date
2013
Publisher
Springer International Publishing AG Switzerland
Number of pages
274
Condition
New
Number of Pages
245
Place of Publication
Cham, Switzerland
ISBN
9783319023779
SKU
V9783319023779
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
About Chakrabarty, Krishnendu; Noia, Brandon
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.
Reviews for Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs