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Pan, Ben U Seng; Martins, Rui Paulo da Silva (University Of Macau); Albuquerque, Jose de (Epifanio da Franca, Chipidea Microelectronics) - Design of Very High-Frequency Multirate Switched-Capacitor Circuits - 9780387261218 - V9780387261218
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Design of Very High-Frequency Multirate Switched-Capacitor Circuits

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Description for Design of Very High-Frequency Multirate Switched-Capacitor Circuits Hardback. Presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique. In order to tackle physical IC imperfections at very high frequency, this work discusses the circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 228 pages, biography. BIC Classification: UY. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 15. Weight in Grams: 542.

Design of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are ... Read more

-Optimum circuit architecture tradeoff analysis
-Simple speed and power trade-off analysis of active elements
-High-order filtering response accuracy with respect to capacitor-ratio mismatches
-Time-interleaved effect with respect to gain and offset mismatch
-Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding
-Stage noise analysis and allocation scheme
-Substrate and supply noise reduction
-Gain-and offset-compensation techniques
-High-bandwidth low-power amplifier design and layout
-Very low timing-skew multiphase generation

Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highestdynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.

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Product Details

Format
Hardback
Publication date
2005
Publisher
Springer-Verlag New York Inc. United States
Number of pages
228
Condition
New
Series
The Springer International Series in Engineering and Computer Science
Number of Pages
228
Place of Publication
New York, NY, United States
ISBN
9780387261218
SKU
V9780387261218
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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