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Formal Equivalence Checking and Design Debugging
Huang, Shi-Yu; Cheng, Kwang-Ting
€ 226.78
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Description for Formal Equivalence Checking and Design Debugging
Paperback. Series: Frontiers in Electronic Testing. Num Pages: 247 pages, biography. BIC Classification: THR; TJFC; UGC; UMA. Category: (G) General (US: Trade). Dimension: 235 x 155 x 13. Weight in Grams: 391.
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error ... Read more
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error ... Read more
Product Details
Format
Paperback
Publication date
2012
Publisher
Springer-Verlag New York Inc. United States
Number of pages
247
Condition
New
Series
Frontiers in Electronic Testing
Number of Pages
229
Place of Publication
New York, NY, United States
ISBN
9781461376064
SKU
V9781461376064
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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