.png){kind=logo}
Stock image for illustration purposes only - book cover, edition or condition may vary.
Direct Transistor-Level Layout for Digital Blocks
Gopalakrishnan, Prakash; Rutenbar, Rob A.
€ 126.29
FREE Delivery in Ireland
Description for Direct Transistor-Level Layout for Digital Blocks
Paperback. Num Pages: 125 pages, biography. BIC Classification: THR; TJFC; UGC. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 8. Weight in Grams: 225.
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation ... Read more
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation ... Read more
Product Details
Format
Paperback
Publication date
2013
Publisher
Springer-Verlag New York Inc. United States
Number of pages
125
Condition
New
Number of Pages
125
Place of Publication
New York, NY, United States
ISBN
9781475779516
SKU
V9781475779516
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
Reviews for Direct Transistor-Level Layout for Digital Blocks