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Rashinkar, Prakash; Paterson, Peter; Singh, Leena - System-on-a-Chip Verification - 9781475774689 - V9781475774689
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System-on-a-Chip Verification

€ 206.19
FREE Delivery in Ireland
Description for System-on-a-Chip Verification paperback. Num Pages: 372 pages, 22 black & white illustrations. BIC Classification: THR; TJFC; UGC; UMA. Category: (G) General (US: Trade). Dimension: 235 x 155 x 21. Weight in Grams: 605.
System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that ... Read more

Product Details

Format
Paperback
Publication date
2013
Publisher
Springer-Verlag New York Inc. United States
Number of pages
372
Condition
New
Number of Pages
372
Place of Publication
New York, NY, United States
ISBN
9781475774689
SKU
V9781475774689
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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