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Low Power Networks-on-chip
. Ed(S): Silvano, Cristina; Lajolo, Marcello; Palermo, Gianluca
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Description for Low Power Networks-on-chip
Hardback. With power consumption now a key design constraint, recent years have seen growing research interest in these networks as an architectural solution for high-speed data transfer. This single-source reference covers some of the most important design techniques. Editor(s): Silvano, Cristina; Lajolo, Marcello; Palermo, Gianluca. Num Pages: 287 pages, biography. BIC Classification: TJFC; UGC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 19. Weight in Grams: 1340.
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
Product Details
Format
Hardback
Publication date
2010
Publisher
Springer-Verlag New York Inc. United States
Number of pages
287
Condition
New
Number of Pages
287
Place of Publication
New York, NY, United States
ISBN
9781441969101
SKU
V9781441969101
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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