Minimizing and Exploiting Leakage in VLSI Design
Jayakumar, Nikhil; Paul, Suganth; Garg, Rajesh
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Description for Minimizing and Exploiting Leakage in VLSI Design
Paperback. This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Num Pages: 241 pages, 37 black & white tables, biography. BIC Classification: TJFC; UGC. Category: (G) General (US: Trade). Dimension: 235 x 155 x 13. Weight in Grams: 379.
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at ... Read more
Show LessProduct Details
Format
Paperback
Publication date
2014
Publisher
Springer-Verlag New York Inc. United States
Number of pages
241
Condition
New
Number of Pages
214
Place of Publication
New York, United States
ISBN
9781489985293
SKU
V9781489985293
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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