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Yield Simulation for Integrated Circuits
D.M.H. Walker
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Description for Yield Simulation for Integrated Circuits
Hardback. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 209 pages, biography. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 14. Weight in Grams: 498.
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and ... Read more
In the summer of 1981 I was asked to consider the possibility of manufacturing a 600,000 transistor microprocessor in 1985. It was clear that the technology would only be capable of manufacturing 100,000-200,000 transistor chips with acceptable yields. The control store ROM occupied approximately half of the chip area, so I considered adding spare rows and columns to increase ROM yield. Laser-programmed polysilicon fuses would be used to switch between good and bad circuits. Since only half the chip area would have redundancy, I was concerned that the increase in yield would not outweigh the increased costs of testing and ... Read more
Product Details
Format
Hardback
Publication date
1987
Publisher
Kluwer Academic Publishers United States
Number of pages
209
Condition
New
Series
The Springer International Series in Engineering and Computer Science
Number of Pages
209
Place of Publication
, United States
ISBN
9780898382440
SKU
V9780898382440
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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