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Constraining Designs for Synthesis and Timing Analysis
Gangadharan, Sridhar; Churiwala, Sanjay
€ 120.97
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Description for Constraining Designs for Synthesis and Timing Analysis
Paperback. This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing. Num Pages: 253 pages, biography. BIC Classification: TJF; TJFC; UYF. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 14. Weight in Grams: 397.
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
This book serves as a hands-on guide to timing constraints in integrated circuit design. Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly. Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.
Product Details
Format
Paperback
Publication date
2013
Publisher
Springer-Verlag New York Inc. United States
Number of pages
253
Condition
New
Number of Pages
226
Place of Publication
New York, United States
ISBN
9781489989161
SKU
V9781489989161
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
About Gangadharan, Sridhar; Churiwala, Sanjay
Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx. Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products ... Read more
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