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Designing 2D and 3D Network-on-chip Architectures
Tatas, Konstantinos; Siozios, Kostas; Jantsch, Axel; Soudris, Dimitrios
€ 128.19
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Description for Designing 2D and 3D Network-on-chip Architectures
Hardcover. This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Num Pages: 278 pages, 65 black & white illustrations, 79 colour illustrations, 12 black & white tables, biograp. BIC Classification: TJFC; UYF. Category: (P) Professional & Vocational. Dimension: 241 x 167 x 21. Weight in Grams: 556.
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
Product Details
Format
Hardback
Publication date
2013
Publisher
Springer-Verlag New York Inc. United States
Number of pages
242
Condition
New
Number of Pages
265
Place of Publication
New York, NY, United States
ISBN
9781461442738
SKU
V9781461442738
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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