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An ASIC Low Power Primer. Analysis, Techniques and Specification.
Chadha, Rakesh; Bhasker, J.
€ 126.98
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Description for An ASIC Low Power Primer. Analysis, Techniques and Specification.
Paperback. This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. It offers a hands-on approach which starts from the ground-up and explains concepts with basic examples. Num Pages: 232 pages, 19 black & white tables, biography. BIC Classification: TJF; TJFC; UYF. Category: (G) General (US: Trade). Dimension: 235 x 155 x 12. Weight in Grams: 361.
This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs). The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent. From analyzing ... Read more
This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs). The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent. From analyzing ... Read more
Product Details
Format
Paperback
Publication date
2015
Publisher
Springer-Verlag New York Inc. United States
Number of pages
232
Condition
New
Number of Pages
218
Place of Publication
New York, United States
ISBN
9781489991508
SKU
V9781489991508
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
About Chadha, Rakesh; Bhasker, J.
J. Bhasker is a well-known expert in the area of hardware description languages and RTL synthesis. He has been chair of two working groups: the IEEE 1076.6 VHDL Synthesis and the IEEE 1364.1 Verilog Synthesis and was awarded the IEEE Computer Society Outstanding Contribution Award in 2005. He is an architect at eSilicon Corporation responsible for the timing of many ... Read more
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