×


 x 

Shopping cart
Pavlov, Andrei; Sachdev, Manoj - CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test - 9781402083624 - V9781402083624
Stock image for illustration purposes only - book cover, edition or condition may vary.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

€ 200.11
FREE Delivery in Ireland
Description for CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test hardcover. This book covers a broad range of topics related to SRAM design and testing. It includes everything from SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. Series: Frontiers in Electronic Testing. Num Pages: 210 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 239 x 166 x 19. Weight in Grams: 468.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Product Details

Format
Hardback
Publication date
2008
Publisher
Springer United States
Number of pages
210
Condition
New
Series
Frontiers in Electronic Testing
Number of Pages
194
Place of Publication
New York, NY, United States
ISBN
9781402083624
SKU
V9781402083624
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

About Pavlov, Andrei; Sachdev, Manoj
Prof. Sachdev has authored several successful books with Springer

Reviews for CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

Goodreads reviews for CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test


Subscribe to our newsletter

News on special offers, signed editions & more!