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Direct Transistor-level Layout for Digital Blocks
Gopalakrishnan, Prakash; Rutenbar, Rob A.
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Description for Direct Transistor-level Layout for Digital Blocks
Hardback. Proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that accommodates demands for device-level flexibility. Useful for CAD tool and circuit designers, this approach aims to capture essential shape-level optimizations and incorporates timing optimization during layout. Num Pages: 125 pages, biography. BIC Classification: TJFC. Category: (G) General (US: Trade); (P) Professional & Vocational; (U) Tertiary Education (US: College). Dimension: 232 x 156 x 9. Weight in Grams: 377.
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation ... Read more
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation ... Read more
Product Details
Format
Hardback
Publication date
2004
Publisher
Springer-Verlag New York Inc. United States
Number of pages
125
Condition
New
Number of Pages
125
Place of Publication
New York, NY, United States
ISBN
9781402076657
SKU
V9781402076657
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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