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Jean . Ed(S): Mermet - VHDL for Simulation, Synthesis and Formal Proofs of Hardware - 9780792392538 - V9780792392538
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VHDL for Simulation, Synthesis and Formal Proofs of Hardware

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Description for VHDL for Simulation, Synthesis and Formal Proofs of Hardware Hardback. Presents recent research on four key issues related to the use of VHDL as a standard for hardware description: simulation of circuits using VHDL; the combination of synthesis and VHDL in designing circuits; the formal verification of VHDL designs; and modelling issues and system level design. Editor(s): Mermet, Jean. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 307 pages, biography. BIC Classification: TJFC; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 235 x 155 x 19. Weight in Grams: 1380.
The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some ... Read more

Product Details

Format
Hardback
Publication date
1992
Publisher
Kluwer Academic Publishers United States
Number of pages
307
Condition
New
Series
The Springer International Series in Engineering and Computer Science
Number of Pages
307
Place of Publication
Dordrecht, Netherlands
ISBN
9780792392538
SKU
V9780792392538
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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