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Sapatnekar, Sachin S.; Saxena, Prashant; Shelar, Rupesh S. (Intel Corporation) - Routing Congestion in VLSI Circuits - 9780387300375 - V9780387300375
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Routing Congestion in VLSI Circuits

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Description for Routing Congestion in VLSI Circuits Hardback. This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. Series: Integrated Circuits and Systems. Num Pages: 250 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 15. Weight in Grams: 1210.
With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path ... Read more

Product Details

Format
Hardback
Publication date
2007
Publisher
Springer-Verlag New York Inc. United States
Number of pages
250
Condition
New
Series
Integrated Circuits and Systems
Number of Pages
250
Place of Publication
New York, NY, United States
ISBN
9780387300375
SKU
V9780387300375
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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