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Delay Fault Testing for VLSI Circuits
Krstic, Angela; Cheng, Kwang-Ting
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Description for Delay Fault Testing for VLSI Circuits
paperback. Series: Frontiers in Electronic Testing. Num Pages: 203 pages, biography. BIC Classification: THR; UGC; UYF. Category: (G) General (US: Trade). Dimension: 235 x 155 x 11. Weight in Grams: 326.
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and ... Read more
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and ... Read more
Product Details
Format
Paperback
Publication date
2012
Publisher
Springer-Verlag New York Inc. United States
Number of pages
203
Condition
New
Series
Frontiers in Electronic Testing
Number of Pages
191
Place of Publication
New York, NY, United States
ISBN
9781461375616
SKU
V9781461375616
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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