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Formal Semantics and Proof Techniques for Optimizing VHDL Models
Umamageswaran, Kothanda; L. Pandey, Sheetanshu; A. Wilsey, Philip
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Description for Formal Semantics and Proof Techniques for Optimizing VHDL Models
Paperback. Num Pages: 158 pages, biography. BIC Classification: PB; THR; UMX. Category: (G) General (US: Trade). Dimension: 235 x 155 x 9. Weight in Grams: 290.
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the ... Read more
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the ... Read more
Product Details
Format
Paperback
Publication date
1998
Publisher
Springer-Verlag New York Inc. United States
Number of pages
158
Condition
New
Number of Pages
158
Place of Publication
New York, NY, United States
ISBN
9781461373315
SKU
V9781461373315
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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