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Low Power Digital CMOS Design
Chandrakasan, Anantha P.; Brodersen, Robert W.
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Description for Low Power Digital CMOS Design
Paperback. Num Pages: 409 pages, biography. BIC Classification: THR; TJFC. Category: (G) General (US: Trade). Dimension: 235 x 155 x 21. Weight in Grams: 646.
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology.
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply ... Read more
Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology.
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply ... Read more
Product Details
Format
Paperback
Publication date
1995
Publisher
Springer-Verlag New York Inc. United States
Number of pages
409
Condition
New
Number of Pages
409
Place of Publication
New York, NY, United States
ISBN
9781461359845
SKU
V9781461359845
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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