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. Ed(S): Tan, Chuan Seng; Gutmann, Ronald J.; Reif, L. Rafael - Wafer Level 3-D Ics Process Technology - 9780387765327 - V9780387765327
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Wafer Level 3-D Ics Process Technology

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Description for Wafer Level 3-D Ics Process Technology Hardback. Wafer Level 3-D Ics Process Technology Editor(s): Tan, Chuan Seng; Gutmann, Ronald J.; Reif, L. Rafael. Series: Integrated Circuits and Systems. Num Pages: 410 pages, 25 black & white tables, biography. BIC Classification: THR. Category: (P) Professional & Vocational. Dimension: 241 x 166 x 23. Weight in Grams: 656.
Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry’s vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides ... Read more

Product Details

Format
Hardback
Publication date
2008
Publisher
Springer-Verlag New York Inc. United States
Number of pages
410
Condition
New
Series
Integrated Circuits and Systems
Number of Pages
410
Place of Publication
New York, NY, United States
ISBN
9780387765327
SKU
V9780387765327
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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