Stock image for illustration purposes only - book cover, edition or condition may vary.
Hierarchical Modeling for VLSI Circuit Testing
Bhattacharya, Debashis; Hayes, John P.
€ 126.46
FREE Delivery in Ireland
Description for Hierarchical Modeling for VLSI Circuit Testing
Hardback. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 160 pages, biography. BIC Classification: T; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 11. Weight in Grams: 940.
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should ... Read more
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should ... Read more
Product Details
Format
Hardback
Publication date
1989
Publisher
Kluwer Academic Publishers United States
Number of pages
160
Condition
New
Series
The Springer International Series in Engineering and Computer Science
Number of Pages
160
Place of Publication
Dordrecht, Netherlands
ISBN
9780792390589
SKU
V9780792390589
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
Reviews for Hierarchical Modeling for VLSI Circuit Testing