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. Ed(S): Narendra, Siva G.; Chandrakasan, Anantha P. - Leakage in Nanometer CMOS Technologies - 9780387257372 - V9780387257372
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Leakage in Nanometer CMOS Technologies

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Description for Leakage in Nanometer CMOS Technologies Hardback. Covers promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles. This title highlights different device design choices that exist to mitigate increases in the leakage components as technology scales. Editor(s): Narendra, Siva G.; Chandrakasan, Anantha P. Series: Integrated Circuits and Systems. Num Pages: 308 pages, biography. BIC Classification: TJ. Category: (UU) Undergraduate. Dimension: 234 x 156 x 19. Weight in Grams: 625.
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., ... Read more

Product Details

Format
Hardback
Publication date
2005
Publisher
Springer-Verlag New York Inc. United States
Number of pages
308
Condition
New
Series
Integrated Circuits and Systems
Number of Pages
308
Place of Publication
New York, NY, United States
ISBN
9780387257372
SKU
V9780387257372
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

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