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Source-Synchronous Networks-on-Chip
Mandal, Ayan; Khatri, Sunil P.
€ 126.32
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Description for Source-Synchronous Networks-on-Chip
Paperback. This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. It provides circuit-level details of the NoC and includes architectural simulations of the NoC. Num Pages: 156 pages, 85 black & white illustrations, 10 colour illustrations, 21 black & white tables, biograp. BIC Classification: TJF; TJFC; UYF. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 9. Weight in Grams: 256.
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
Product Details
Format
Paperback
Publication date
2016
Publisher
Springer-Verlag New York Inc. United States
Number of pages
156
Condition
New
Number of Pages
143
Place of Publication
New York, United States
ISBN
9781493948178
SKU
V9781493948178
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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