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High-Level Verification: Methods and Tools for Verification of System-Level Designs
Kundu, Sudipta, Lerner, Sorin, Gupta, Rajesh K.
€ 127.73
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Description for High-Level Verification: Methods and Tools for Verification of System-Level Designs
Hardcover. The growing complexity of the design process for systems on chip (SOCs) allows the use of more demanding computing languages, with a principle goal being verification at a higher level of abstraction. This book focuses on these high-level verification methods. Num Pages: 167 pages, 6 black & white tables, biography. BIC Classification: TBD; TJFC. Category: (P) Professional & Vocational. Dimension: 247 x 163 x 17. Weight in Grams: 420. 184 pages, black & white illustrations. The growing complexity of the design process for systems on chip (SOCs) allows the use of more demanding computing languages, with a principle goal being verification at a higher level of abstraction. This book focuses on these high-level verification methods. Cateogry: (P) Professional & Vocational. BIC Classification: TBD; TJFC. Dimension: 247 x 163 x 17. Weight: 420.
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies ... Read more
Given the growing size and heterogeneity of Systems on Chip (SOC), the design process from initial specification to chip fabrication has become increasingly complex. This growing complexity provides incentive for designers to use high-level languages such as C, SystemC, and SystemVerilog for system-level design. While a major goal of these high-level languages is to enable verification at a higher level of abstraction, allowing early exploration of system-level designs, the focus so far for validation purposes has been on traditional testing techniques such as random testing and scenario-based testing. This book focuses on high-level verification, presenting a design methodology that relies ... Read more
Product Details
Format
Hardback
Publication date
2011
Publisher
Springer
Number of pages
178
Condition
New
Number of Pages
167
Place of Publication
New York, NY, United States
ISBN
9781441993588
SKU
V9781441993588
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
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