VLSI Placement and Global Routing Using Simulated Annealing
C. Sechen
€ 199.99
FREE Delivery in Ireland
Description for VLSI Placement and Global Routing Using Simulated Annealing
Hardback. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 278 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609.
From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of ... Read more
From my B.E.E degree at the University of Minnesota and right through my S.M. degree at M.I.T., I had specialized in solid state devices and microelectronics. I made the decision to switch to computer-aided design (CAD) in 1981, only a year or so prior to the introduction of the simulated annealing algorithm by Scott Kirkpatrick, Dan Gelatt, and Mario Vecchi of the IBM Thomas 1. Watson Research Center. Because Prof. Alberto Sangiovanni-Vincentelli, my UC Berkeley advisor, had been a consultant at IBM, I re ceived a copy of the original IBM internal report on simulated annealing approximately the day of ... Read more
Product Details
Format
Hardback
Publication date
1988
Publisher
Kluwer Academic Publishers United States
Number of pages
278
Condition
New
Series
The Springer International Series in Engineering and Computer Science
Number of Pages
278
Place of Publication
, United States
ISBN
9780898382815
SKU
V9780898382815
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
Reviews for VLSI Placement and Global Routing Using Simulated Annealing